www.siliconstandard.com 1 of 4 SSM2306N re v . 2.02 3 /16 /2004 n-channel enhancement-mode power mosfet capable of 2.5v gate-drive bv dss 20v lower on-resistance r ds(on) 32mw surface-mount package i d 5.3a description absolute maximum ratings symbol units v ds v v gs v i d @ t a =25c i d @ t a =70c i dm a p d @ t a =25c w/c t stg t j symbol value unit rthj-a thermal resistance junction-ambient 3 max. 90 c/w parameter rating drain-source voltage 20 gate-source voltage continuous drain current 3 , v gs @ 4.5v 5.3 a continuous drain current 3 , v gs @ 4.5v 4.3 a pulsed drain current 1,2 10 total power dissipation 1.38 w -55 to 150 c operating junction temperature range -55 to 150 c linear derating factor 0.01 thermal data parameter storage temperature range 12 g d s d g s sot-23 power mosfets from silicon standard utilize advanced processing techniques to achieve the lowest possible on-resistance in an extremely efficient and cost-effective device. the sot-23 package is widely used for commercial and industrial applications.
www.siliconstandard.com 2 of 4 re v . 2.02 3 /16 /2004 SSM2306N electrical characteristics @ t j =25 o c (unless otherwise specified) symbol parameter test conditions min. typ. max. units bv dss drain-source breakdown voltage v gs =0v, i d =250ua 20 - - v dbv dss / d t j breakdown voltage temperature coefficient reference to 25c, i d =1ma - 0.1 - v/c r ds(on) static drain-source on-resistance v gs =10v, i d =5.5a - - 27 mw v gs =4.5v, i d =5.3a - - 32 mw v gs =2.5v, i d =2.6a - - 50 mw v gs(th) gate threshold voltage v ds =v gs , i d =250ua 0.5 - - v g fs forward transconductance v ds =5v, i d =5.3a - 13 - s i dss drain-source leakage current (t j =25 o c) v ds =20v, v gs =0v - - 1 ua drain-source leakage current (t j =55 o c) v ds =16v ,v gs =0v - - 10 ua i gss gate-source leakage v gs =- - na q g total gate charge 2 i d =5.3a - 8.7 - nc q gs gate-source charge v ds =10v - 1.5 - nc q gd gate-drain ("miller") charge v gs =4.5v - 3.6 - nc t d(on) turn-on delay time 2 v ds =15v - 6 - ns t r rise time i d =1a - 14 - ns t d(off) turn-off delay time r g =2w ,v gs =10v - 18.4 - ns t f fall time r d =15w - 2.8 - ns c iss input capacitance v gs =0v - 575 - pf c oss output capacitance v ds =10v - 120 - pf c rss reverse transfer capacitance f=1.0mhz - 92.3 - pf source-drain diode symbol parameter test conditions min. typ. max. units v sd forward on voltage 2 i s =1.2a, v gs =0v - - 1.2 v trr reverse recovery time i s =5a, v gs =0v, - 16.8 - ns qrr reverse recovery charge di/dt=100a/s - 11 - nc notes: 1.pulse width limited by max. junction temperature. 2.pulse width < 300us , duty cycle < 2%. 3.surface mounted on 1 in 2 copper pad of fr4 board ; 270c/w when mounted on min. copper pad. 12 v 100
www.siliconstandard.com 3 of 4 re v . 2.02 3 /16 /2004 SSM2306N fig 1. typical output characteristics fig 2. typical output characteristics fig 3. on-resistance vs. gate voltage fig 4. normalized on-resistance vs. junction temperature fig 5. forward characteristic of fig 6. gate threshold voltage vs. reverse diode junction temperature 0 20 40 60 80 01234567 v ds , drain-to-source voltage (v) i d , drain current (a) t a =25 o c v g =2.5v 4.0v 5.0v 4.5v 0 10 20 30 40 50 012345678 v ds , drain-to-source voltage (v) i d , drain current (a) t a =150 o c 4.0v v g =2.5v 4.5v 5.0v 0.01 0.1 1 10 100 0 0.4 0.8 1.2 1.6 v sd , source-to-drain voltage (v) i s (a) t j =25 o c t j =150 o c 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -50 0 50 100 150 t j , junction temperature ( o c ) v gs(th) (v) 0.6 0.8 1.0 1.2 1.4 1.6 1.8 -50 0 50 100 150 t j , junction temperature ( o c) normalized r ds(on) v g =4.5v i d =5.3a 20 40 60 80 100 1357911 v gs , gate-to-source voltage (v) r ds(on) (m ) i d =5.3a t a =25 o c
www.siliconstandard.com 4 of 4 in formation furnished by silicon standard corporation is believed to be accurate and reliable. however, silicon standard corporation makes no guarantee or warranty, expre ss or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. silicon standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. no license is granted, whether expressly or by im plication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of silicon standard corporation or any third parties. re v . 2.02 3 /16 /2004 SSM2306N 0 2 4 6 8 10 12 14 0 5 10 15 20 25 q g , total gate charge (nc) v gs , gate to so ur ce voltage (v) v ds =16v i d =5.3a 10 100 1000 1 5 9 13 17 21 25 29 v ds , drain-to-source voltage (v) c (pf) f =1.0mhz ciss coss crss 0.01 0.1 1 10 100 0.1 1 10 100 v ds , drain-to-source voltage (v) i d (a) t a =25 o c single pulse 1s 1ms 10ms 100ms dc 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 10 100 1000 t , pulse width (s) normalized thermal response (r thja ) 0.01 0.05 0.1 0.2 duty=0.5 single pulse p dm duty factor = t/t peak t j = p dm x r thja + t a t t rthja = 270 # ## # /w 0.75x rated v to the oscilloscope - + 10 v d g s v ds v gs r g r d 0.5 x rated v ds to the oscilloscope - + d g s v ds v gs i d i g 1~ 3 ma fig 11. switching time circuit fig 12. gate charge circuit fig 7. gate charge characteristics fig 8. typical capacitance characteristics fig 9. maximum safe operating area fig 10. effective transient thermal impedance
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